CPC H01L 23/5329 (2013.01) [H01L 23/5226 (2013.01); H10B 12/30 (2023.02)] | 18 Claims |
1. A semiconductor memory device comprising:
semiconductor substrate;
word lines extending in a first direction on the semiconductor substrate;
bit line structures extending across the word lines, the bit line structures extending in a second direction crossing the first direction;
contact pad structures between the word lines and between the bit line structures; and
spacers between the bit line structures and the contact pad structures, the spacers comprising a boron nitride layer comprising at least one of amorphous material and nanocrystalline material,
wherein
the bit line structures comprise a polysilicon pattern, a barrier/liner patter, a metal pattern, and a hard mask pattern, which are sequentially stacked on the semiconductor substrate, and
the spacers overlap the polysilicon pattern, the barrier/liner pattern, and the metal pattern with respect to the first direction.
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