US 12,080,649 B2
Semiconductor memory device and apparatus including the same
Hyeonjin Shin, Suwon-si (KR); Minhyun Lee, Suwon-si (KR); Changseok Lee, Gwacheon-si (KR); Kyung-Eun Byun, Seongnam-si (KR); Hyeonsuk Shin, Ulsan (KR); and Seokmo Hong, Ulsan (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR); and UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY), Ulsan (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR); and UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY), Ulsan (KR)
Filed on Aug. 23, 2022, as Appl. No. 17/893,349.
Application 17/893,349 is a continuation of application No. 17/082,530, filed on Oct. 28, 2020, granted, now 11,424,186, issued on Aug. 23, 2022.
Claims priority of application No. 10-2019-0135755 (KR), filed on Oct. 29, 2019; and application No. 10-2020-0054106 (KR), filed on May 6, 2020.
Prior Publication US 2022/0415800 A1, Dec. 29, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 23/522 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/5329 (2013.01) [H01L 23/5226 (2013.01); H10B 12/30 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
semiconductor substrate;
word lines extending in a first direction on the semiconductor substrate;
bit line structures extending across the word lines, the bit line structures extending in a second direction crossing the first direction;
contact pad structures between the word lines and between the bit line structures; and
spacers between the bit line structures and the contact pad structures, the spacers comprising a boron nitride layer comprising at least one of amorphous material and nanocrystalline material,
wherein
the bit line structures comprise a polysilicon pattern, a barrier/liner patter, a metal pattern, and a hard mask pattern, which are sequentially stacked on the semiconductor substrate, and
the spacers overlap the polysilicon pattern, the barrier/liner pattern, and the metal pattern with respect to the first direction.