| CPC H01L 23/5283 (2013.01) [H01L 23/5226 (2013.01); H01L 23/535 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02)] | 18 Claims |
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1. A memory device, comprising:
a base structure having string driver circuitry, the string driver circuitry comprising:
pairs of even rows of string driver transistors; and
pairs of odd rows of string driver transistors horizontally alternating with the pairs of the even rows of string driver transistors;
a memory structure overlying the base structure and comprising blocks each having a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the blocks comprising:
even blocks vertically overlying the pairs of even rows of string driver transistors, each even block comprising at least one stadium structure within horizontal boundaries of the string driver circuitry of the base structure, the at least one stadium structure comprising opposing staircase structures each having steps comprising horizontal ends of the tiers of the even block; and
odd blocks vertically overlying the pairs of odd rows of string driver transistors and horizontally alternating with the even blocks, each odd block comprising at least one additional stadium structure within horizontal boundaries of the string driver circuitry of the base structure, the at least one additional stadium structure comprising additional opposing staircase structures each having additional steps comprising horizontal ends of the tiers of the odd block;
first conductive routing structures coupling the conductive structures of the even blocks with the string driver transistors of first even rows of the pairs of even rows of string driver transistors and with the string driver transistors of first odd rows of the pairs of odd rows of string driver transistors; and
second conductive routing structures coupling the conductive structures of the odd blocks with the string driver transistors of second even rows of the pairs of even rows of string driver transistors and with the string driver transistors of second odd rows of the pairs of odd rows of string driver transistors.
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