US 12,080,643 B2
Integrated circuit structures having differentiated interconnect lines in a same dielectric layer
Travis W. Lajoie, Forest Grove, OR (US); Abhishek A. Sharma, Hillsboro, OR (US); Juan G. Alzate Vinasco, Tigard, OR (US); Chieh-Jen Ku, Hillsboro, OR (US); Shem O. Ogadhoh, Beaverton, OR (US); Allen B. Gardiner, Portland, OR (US); Blake C. Lin, Portland, OR (US); Yih Wang, Portland, OR (US); Pei-Hua Wang, Beaverton, OR (US); Jack T. Kavalieros, Portland, OR (US); Bernhard Sell, Portland, OR (US); and Tahir Ghani, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2019, as Appl. No. 16/583,691.
Prior Publication US 2021/0098373 A1, Apr. 1, 2021
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 21/76816 (2013.01); H01L 21/76829 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate; and
a plurality of conductive interconnect lines in the ILD layer, the plurality of conductive interconnect lines comprising:
a first conductive interconnect line; and
a second conductive interconnect line immediately adjacent to the first conductive interconnect line, the second conductive interconnect line having a bottommost surface above a bottommost surface of the first conductive interconnect line, and the second conductive interconnect line having an uppermost surface below an uppermost surface of the first conductive interconnect line, wherein the ILD layer is on the uppermost surface of the second conductive interconnect line,
wherein the second conductive interconnect line has a width less than a width of the first conductive interconnect line.
 
7. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
an inter-layer dielectric (ILD) layer above a substrate; and
a plurality of conductive interconnect lines in the ILD layer, the plurality of conductive interconnect lines comprising:
a first conductive interconnect line; and
a second conductive interconnect line immediately adjacent to the first conductive interconnect line, the second conductive interconnect line having a bottommost surface above a bottommost surface of the first conductive interconnect line, and the second conductive interconnect line having an uppermost surface below an uppermost surface of the first conductive interconnect line, wherein the ILD layer is on the uppermost surface of the second interconnect line,
wherein the second conductive interconnect line has a width less than a width of the first conductive interconnect line.