US 12,080,639 B2
Contact over active gate structures with metal oxide layers to inhibit shorting
Rami Hourani, Beaverton, OR (US); Manish Chandhok, Beaverton, OR (US); Richard E. Schenker, Portland, OR (US); Florian Gstrein, Portland, OR (US); Leonard P. Guler, Hillsboro, OR (US); Charles H. Wallace, Portland, OR (US); Paul A. Nyhus, Portland, OR (US); Curtis Ward, Forest Grove, OR (US); Mohit K. Haran, Hillsboro, OR (US); and Reken Patel, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 23, 2019, as Appl. No. 16/579,077.
Prior Publication US 2021/0090990 A1, Mar. 25, 2021
Int. Cl. H01L 29/417 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/66 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/02175 (2013.01); H01L 21/76816 (2013.01); H01L 21/76897 (2013.01); H01L 23/66 (2013.01); H01L 2223/6677 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a plurality of gate structures, each of the gate structures including a gate insulating layer thereon;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, a portion of one of the plurality of trench contact structures having a metal oxide layer thereon;
an interlayer dielectric material over the plurality of gate structures and over the plurality of conductive trench contact structures;
an opening in the interlayer dielectric material and in the gate insulating layer of a corresponding one of the plurality of gate structures, wherein the metal oxide layer is confined to the opening; and
a conductive via in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.