US 12,080,636 B2
Semiconductor package and manufacturing method of semiconductor package
Koichi Igarashi, Kanagawa (JP)
Assigned to SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
Appl. No. 17/310,851
Filed by SONY SEMICONDUCTOR SOLUTIONS CORPORATION, Kanagawa (JP)
PCT Filed Dec. 9, 2019, PCT No. PCT/JP2019/048095
§ 371(c)(1), (2) Date Aug. 26, 2021,
PCT Pub. No. WO2020/183822, PCT Pub. Date Sep. 17, 2020.
Claims priority of application No. 2019-045100 (JP), filed on Mar. 12, 2019.
Prior Publication US 2022/0084921 A1, Mar. 17, 2022
Int. Cl. H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 27/146 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 23/49822 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 27/14618 (2013.01); H01L 2224/0219 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/0347 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/16225 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor substrate and a pad provided on one surface of the semiconductor substrate;
an insulating layer configured to cover a different surface of the semiconductor substrate;
a metal layer configured to cover the insulating layer;
an interposer substrate on which a wire, configured to connect to the pad, is formed;
a signal transmission solder ball configured to join the wire and a predetermined mounting substrate to transmit a predetermined electrical signal; and
a solder member configured to join the metal layer and the predetermined mounting substrate.