CPC H01L 23/481 (2013.01) [H01L 21/743 (2013.01); H01L 23/34 (2013.01); H01L 23/50 (2013.01); H01L 23/544 (2013.01); H01L 27/0207 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/0886 (2013.01); H01L 27/11807 (2013.01); H01L 29/1066 (2013.01); H01L 29/66272 (2013.01); H01L 29/66704 (2013.01); H01L 29/66825 (2013.01); H01L 29/66901 (2013.01); H01L 29/732 (2013.01); H01L 29/7841 (2013.01); H01L 29/808 (2013.01); H10B 12/09 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H01L 27/0623 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/16152 (2013.01); H10B 63/30 (2023.02); H10B 63/845 (2023.02)] | 20 Claims |
1. A 3D semiconductor device, the device comprising:
a first level comprising a plurality of first metal layers;
a second level,
wherein said second level overlays said first level,
wherein said second level comprises at least one single crystal silicon layer,
wherein said second level comprises a plurality of transistors,
wherein each transistor of said plurality of transistors comprises a single crystal channel,
wherein said second level comprises a plurality of second metal layers,
wherein said plurality of second metal layers comprise interconnections between said transistors of said plurality of transistors, and
wherein said second level is overlaid by a first isolation layer; and
a connective path from said plurality of transistors to said plurality of first metal layers,
wherein said connective path comprises a via disposed through at least said single crystal silicon layer,
wherein each of at least one of said plurality of transistors comprises a two sided gate, and
wherein said single crystal silicon layer thickness is less than two microns.
|