US 12,080,625 B2
Semiconductor package with releasable isolation layer protection
Li Fong Chong, Melaka (MY); Yee Beng Daryl Yeow, Melaka (MY); Chii Shang Hong, Melaka (MY); Azlina Kassim, Melaka (MY); and Hui Kin Lit, Melaka (MY)
Assigned to Infineon Technologies Austria AG, Villach (AT)
Filed by Infineon Technologies Austria AG, Villach (AT)
Filed on Aug. 18, 2023, as Appl. No. 18/235,668.
Application 18/235,668 is a division of application No. 17/355,342, filed on Jun. 23, 2021, granted, now 11,791,238.
Prior Publication US 2023/0395462 A1, Dec. 7, 2023
Int. Cl. H01L 23/495 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/433 (2006.01)
CPC H01L 23/4334 (2013.01) [H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/315 (2013.01); H01L 23/49503 (2013.01); H01L 23/562 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48245 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor package, comprising a package body that comprises an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than that of the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die; and
a releasable layer affixed to the semiconductor package;
wherein a first outer face of the package body comprises a first surface of the isolation structure,
wherein the releasable layer at least partially covers the first surface of the isolation structure, and
wherein the releasable layer is releasable from the semiconductor package.