US 12,080,622 B2
Semiconductor structure and method of wafer bonding
Chia-Liang Liao, Yunlin County (TW); Purakh Raj Verma, Singapore (SG); Ching-Yang Wen, Singapore (SG); and Chee Hau Ng, Singapore (SG)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Apr. 18, 2023, as Appl. No. 18/136,329.
Application 18/136,329 is a continuation of application No. 16/924,206, filed on Jul. 9, 2020, granted, now 11,670,567.
Prior Publication US 2023/0268246 A1, Aug. 24, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/373 (2006.01); H01L 21/48 (2006.01); H01L 23/15 (2006.01)
CPC H01L 23/3735 (2013.01) [H01L 21/4871 (2013.01); H01L 23/15 (2013.01); H01L 23/3736 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a glass substrate comprising a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top; and
a device structure comprising at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate, wherein an entire surface of the device structure is bonded with an entire surface of the silicon nitride layer.