US 12,080,614 B2
Lidded semiconductor package
Shih-Chao Chiu, Hsinchu (TW); Chi-Yuan Chen, Hsinchu (TW); Wen-Sung Hsu, Hsinchu (TW); Ya-Jui Hsieh, Hsinchu (TW); Yao-Pang Hsu, Hsinchu (TW); and Wen-Chun Huang, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsin-Chu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Oct. 5, 2021, as Appl. No. 17/493,853.
Claims priority of provisional application 63/177,992, filed on Apr. 22, 2021.
Claims priority of provisional application 63/105,377, filed on Oct. 26, 2020.
Prior Publication US 2022/0130734 A1, Apr. 28, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 23/40 (2006.01); H01L 23/473 (2006.01); H05K 5/00 (2006.01); H05K 5/02 (2006.01); H05K 5/03 (2006.01)
CPC H01L 23/31 (2013.01) [H01L 23/4006 (2013.01); H01L 23/473 (2013.01); H05K 5/0052 (2013.01); H05K 5/0221 (2013.01); H05K 5/03 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate having a top surface and a bottom surface;
a semiconductor die mounted on the top surface of the substrate; and
a two-part lid mounted on a perimeter of the top surface of the substrate and housing the semiconductor die, wherein the lid comprises an annular lid base and a cover plate removably installed on the annular lid base, wherein the annular lid base comprises vertical walls spaced apart from the semiconductor die and an annular, horizontal inner flange inwardly protruding beyond the vertical walls, wherein the horizontal inner flange overlaps with a peripheral portion of the semiconductor die.