US 12,080,608 B2
Self-limiting manufacturing techniques to prevent electrical shorts in a complementary field effect transistor (CFET)
Xi-Wei Lin, Fremont, CA (US); and Victor Moroz, Saratoga, CA (US)
Assigned to Synopsys, Inc., Sunnyvale, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Jul. 9, 2021, as Appl. No. 17/372,254.
Claims priority of provisional application 63/053,503, filed on Jul. 17, 2020.
Prior Publication US 2022/0020647 A1, Jan. 20, 2022
Int. Cl. H01L 21/8238 (2006.01)
CPC H01L 21/823871 (2013.01) [H01L 21/823885 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method comprising:
adding a blocking material into a vertical region of a structure having a lower level silicon epitaxial region and a silicon substrate located below the lower level silicon epitaxial region in a lower level of the structure, the blocking material being located below and in contact with a lower portion of the lower level silicon epitaxial region, the blocking material separating the silicon substrate from the vertical region;
adding an insulating material to an open area within the vertical region to surround a portion of at least the lower level silicon epitaxial region;
performing a first etch to (i) remove a portion of the added insulating material, (ii) expose a contact surface of the lower level silicon epitaxial region and (iii) provide a vertical opening within the vertical region, the first etch leaving at least a portion of the blocking material, such that the silicon substrate region is not exposed to the vertical opening; and
filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the lower level silicon epitaxial region, the at least the portion of the blocking material remaining below the conductive material to prevent contact between the conductive material and the silicon substrate located below the lower level silicon epitaxial region.