CPC H01L 21/823814 (2013.01) [H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/266 (2013.01); H01L 21/30604 (2013.01); H01L 21/308 (2013.01); H01L 21/823821 (2013.01); H01L 21/823828 (2013.01); H01L 21/823864 (2013.01); H01L 27/0924 (2013.01); H01L 29/0847 (2013.01); H01L 29/167 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] | 20 Claims |
1. A method, comprising:
providing a workpiece having a semiconductor substrate with a first circuit area and a second circuit area;
forming a first active region within the first circuit area and a second active region within the second circuit area;
forming a first gate structure on the first active region and a second gate structure on the second active region;
introducing a doping species to the first active region but not the second active region;
performing an etching process, thereby simultaneously recessing both first source/drain regions of the first active region and second source/drain regions of the second active region at a same etch rate; and
thereafter, epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.
|