CPC H01L 21/823475 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 23/481 (2013.01); H01L 23/53295 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/785 (2013.01)] | 24 Claims |
1. An integrated circuit structure, comprising:
a vertical stack of horizontal nanowires;
a gate structure over the vertical stack of horizontal nanowires, the gate structure surrounding a channel region of each of the vertical stack of horizontal nanowires;
a first source or drain structure laterally adjacent to a first end of the vertical stack of horizontal nanowires;
a second source or drain structure laterally adjacent to a second end of the vertical stack of horizontal nanowires, the second end opposite the first end; and
a backside interconnect vertically beneath and electrically coupled to one of the first source or drain structure or the second source or drain structure, wherein the backside interconnect has a lateral width greater than a lateral width of the one of the first source or drain structure or the second source or drain structure.
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