US 12,080,604 B2
Gate-all-around semiconductor device and method
Chia-Hao Pao, Hsinchu (TW); Chih-Chuan Yang, Tainan (TW); Shih-Hao Lin, Hsinchu (TW); Kian-Long Lim, Hsinchu (TW); Chih-Wei Lee, Hsinchu (TW); Chien-Yuan Chen, Hsinchu (TW); Jo-Chun Hung, Hsinchu (TW); Yung-Hsiang Chan, Hsinchu (TW); Yu-Kuan Lin, Hsinchu (TW); and Lien-Jung Hung, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,163.
Application 18/362,163 is a continuation of application No. 17/387,636, filed on Jul. 28, 2021, granted, now 11,791,214.
Claims priority of provisional application 63/188,507, filed on May 14, 2021.
Prior Publication US 2023/0411216 A1, Dec. 21, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823481 (2013.01); H01L 21/823821 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/6681 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A semiconductor structure, comprising:
a dummy fin disposed over an isolation structure;
a stack of channel layers adjacent to the dummy fin, wherein widths of the channel layers of the stack of channel layers increase as they are further away from an underlying substrate;
a first high-k dielectric portion wrapping around a first channel layer of the stack of channel layers;
a second high-k dielectric portion wrapping around a second channel layer of the stack of channel layers, the second channel layer closer to the underlying substrate than the first channel layer; and
a third high-k dielectric portion disposed on sidewalls of the dummy fin;
wherein a first lateral distance between the first high-k dielectric portion and the third high-k dielectric portion is less than a second lateral distance between the second high-k dielectric portion and the third high-k dielectric portion.