US 12,080,600 B2
Semiconductor device and method to minimize stress on stack via
Yaojian Lin, Jiangyin (CN); and Seng Guan Chow, Singapore (SG)
Assigned to STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed by STATS ChipPAC Pte. Ltd., Singapore (SG)
Filed on Sep. 2, 2020, as Appl. No. 17/010,610.
Application 17/010,610 is a continuation of application No. 15/169,095, filed on May 31, 2016, granted, now 10,804,153.
Application 15/169,095 is a continuation in part of application No. 14/305,560, filed on Jun. 16, 2014, abandoned.
Prior Publication US 2020/0402855 A1, Dec. 24, 2020
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/66 (2006.01); H01L 21/78 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 22/14 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/562 (2013.01); H01L 24/03 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 24/02 (2013.01); H01L 24/04 (2013.01); H01L 24/05 (2013.01); H01L 2224/02125 (2013.01); H01L 2224/02145 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02351 (2013.01); H01L 2224/0236 (2013.01); H01L 2224/02377 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/024 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05011 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05111 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05164 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05169 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05172 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05551 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13113 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/92 (2013.01); H01L 2224/94 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01073 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/0132 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/014 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/0535 (2013.01); H01L 2924/05432 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/059 (2013.01); H01L 2924/0635 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/10252 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/10322 (2013.01); H01L 2924/10324 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10335 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/1207 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/14335 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/186 (2013.01); H01L 2924/351 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing a first insulating layer over the semiconductor die;
forming a first via in the first insulating layer over a contact pad of the semiconductor die;
disposing a first conductive layer over the first insulating layer and into the first via;
disposing a second insulating layer over the first insulating layer and first conductive layer;
forming a second via in the second insulating layer over the first conductive layer and aligned with the first via; and
disposing a second conductive layer over the first conductive layer and second insulating layer with an opening in the second conductive layer extending across the first via, wherein a width of the opening is greater than a width of the first via and the opening is off-center with respect to the second via.