US 12,080,592 B2
Film stack simplification for high aspect ratio patterning and vertical scaling
Hui-Jung Wu, Pleasanton, CA (US); Bart J. van Schravendijk, Palo Alto, CA (US); Mark Naoshi Kawaguchi, San Carlos, CA (US); Gereng Gunawan, Saratoga, CA (US); Jay E. Uglow, Livermore, CA (US); Nagraj Shankar, Tualatin, OR (US); Gowri Channa Kamarthy, Pleasanton, CA (US); Kevin M. McLaughlin, Sherwood, OR (US); Ananda K. Banerji, West Linn, OR (US); Jialing Yang, Sherwood, OR (US); John Hoang, Fremont, CA (US); Aaron Lynn Routzahn, Fremont, CA (US); Nathan Musselwhite, San Jose, CA (US); Meihua Shen, Fremont, CA (US); Thorsten Bernd Lill, Kalaheo, HI (US); Hao Chi, San Mateo, CA (US); and Nicholas Dominic Altieri, San Mateo, CA (US)
Assigned to Lam Research Corporation, Fremont, CA (US)
Appl. No. 17/250,835
Filed by Lam Research Corporation, Fremont, CA (US)
PCT Filed Sep. 10, 2019, PCT No. PCT/US2019/050369
§ 371(c)(1), (2) Date Mar. 10, 2021,
PCT Pub. No. WO2020/055837, PCT Pub. Date Mar. 19, 2020.
Claims priority of provisional application 62/729,323, filed on Sep. 10, 2018.
Prior Publication US 2022/0051938 A1, Feb. 17, 2022
Int. Cl. H01L 21/336 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 29/788 (2006.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01)
CPC H01L 21/76846 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02263 (2013.01); H01L 21/31105 (2013.01); H01L 21/76816 (2013.01); H01L 29/7889 (2013.01); H10B 41/20 (2023.02); H10B 41/35 (2023.02)] 8 Claims
OG exemplary drawing
 
1. A method comprising:
providing a semiconductor substrate;
depositing a metal-free multi-layer stack having at least three different materials, at least one of the three different materials being a sacrificial layer;
etching a trench or via in the metal-free multi-layer stack having the at least three different materials;
recessing one of the at least three different materials after etching the trench or via to form a recessed region of the via;
depositing a dielectric or semiconductor material into the trench or via;
etching back the dielectric or semiconductor material in the trench or via to form smooth sidewalls, leaving the dielectric or semiconductor material in the recessed region; and
prior to selectively etching the sacrificial layer, depositing a gate material into the trench or via, and recessing a dielectric material in sidewalls of the trench or via in the metal-free multi-layer stack;
selectively etching the sacrificial layer relative to other materials of the metal-free multi-layer stack to form at least one space between layers of the metal-free multi-layer stack; and
depositing metal in the at least one space to form a metal-containing multi-layer stack having a trench or via etched therein.