	US 12,080,589 B2
	Formation method of semiconductor structure
Weijun Wang, Shanghai (CN); and Hong Lin, Shanghai (CN)
Assigned to SHANGHAI IC R&D CENTER CO., LTD., Shanghai (CN)
Appl. No. 17/284,849
Filed by SHANGHAI IC R&D CENTER CO., LTD., Shanghai (CN)
PCT Filed Sep. 6, 2019, PCT No. PCT/CN2019/104666 § 371(c)(1), (2) Date Apr. 13, 2021, PCT Pub. No. WO2020/048524, PCT Pub. Date Mar. 12, 2020.
Claims priority of application No. 201811044219.6 (CN), filed on Sep. 7, 2018.
Prior Publication US 2022/0059402 A1, Feb. 24, 2022
Int. Cl. H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01)

CPC H01L 21/76224 (2013.01) [H01L 21/02323 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01)]

10 Claims

1. A formation method of a semiconductor structure, comprising the following steps in sequence:

providing a semiconductor substrate, and forming a hard mask layer on the semiconductor substrate;

forming a photo-lithographic pattern on the hard mask layer;

using the photo-lithographic pattern as a mask and patterning the hard mask layer and the semiconductor substrate below the hard mask layer to obtain a hard mask pattern and a fin structure with a steep sidewall profile;

forming a protective layer on a sidewall surface of the fin structure;

using the fin structure as a mask to etch the semiconductor substrate located below to form isolation structure trenches;

performing a modified treatment on exposed surfaces of the isolation structure trenches to form a modified layer; wherein a thickness of the modified layer and a thickness of the protective layer achieve a substantially consistent thickness;

removing the protective layer and the modified layer simultaneously;

filling a dielectric layer in the isolation structure trenches till to cover the fin structure;

planarizing the dielectric layer till to expose the hard mask layer on the top of the fin structure;

performing a trench etching process to the dielectric layer and forming the semiconductor structure having the fin structure and an isolation structure with sloped sidewalls.