US 12,080,560 B2
Methods for forming dielectric layer in forming semiconductor device
Yonggang Yang, Wuhan (CN); and Xiaohong Zhou, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Oct. 11, 2021, as Appl. No. 17/498,337.
Application 17/498,337 is a continuation of application No. PCT/CN2021/115993, filed on Sep. 1, 2021.
Prior Publication US 2023/0069697 A1, Mar. 2, 2023
Int. Cl. H01L 21/311 (2006.01); H01L 21/3105 (2006.01)
CPC H01L 21/31144 (2013.01) [H01L 21/31053 (2013.01); H01L 21/31116 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure over a staircase region and an array region;
forming a dielectric material layer over the array region and the staircase region;
forming an etch mask layer over the dielectric material layer;
planarizing a first surface of the etch mask layer away from the dielectric material layer to fully remove a portion of the etch mask layer over the array region and form a remaining portion of the etch mask layer over the staircase region; and
etching the dielectric material layer and the remaining portion of the etch mask layer to form a dielectric layer over the staircase region and the array region.
 
13. A method for forming a three-dimensional (3D) memory device, comprising:
forming a stack structure over a staircase region and an array region;
forming a dielectric material layer over the array region and the staircase region;
forming an etch mask layer over the dielectric material layer that is arranged over the array region and the staircase region, the etch mask layer comprising a first portion over the array region and a second portion over the staircase region, and the second portion of the etch mask layer being thicker than the first portion of the etch mask layer;
removing the first portion of the etch mask layer, over the array region, from the etch mask layer to form an etch mask portion over a portion of the dielectric material layer over the staircase region, the etch mask portion being part of the second portion of the etch mask layer over the staircase region; and
etching the dielectric material layer and the etch mask portion to form a dielectric layer over the staircase region and the array region.