CPC H01L 21/28194 (2013.01) [H01L 21/0228 (2013.01); H01L 21/02477 (2013.01); H01L 21/823462 (2013.01); H01L 29/42364 (2013.01); H01L 29/78 (2013.01)] | 20 Claims |
1. A method, comprising:
forming a 2-D material semiconductor layer over a substrate;
forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes;
forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by a physical deposition process;
forming a second gate dielectric layer over the first gate dielectric layer by a chemical deposition process, wherein a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer, and wherein the chemical deposition process comprises an atomic layer deposition (ALD) process, wherein the ALD process comprises at least one ALD cycle each comprising:
injecting an oxygen source into an ALD chamber for a first duration;
halting injecting the oxygen source into the ALD chamber;
purging the oxygen source in the ALD chamber;
injecting a metal source into the ALD chamber for a second duration;
halting injecting the metal source into the ALD chamber; and
purging the metal source in the ALD chamber, wherein a time duration between halting injecting the oxygen source and beginning purging the oxygen source is less than a time duration between halting injecting the metal source and beginning purging the metal source; and
forming a gate electrode over the second gate dielectric layer.
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