US 12,080,556 B2
Fin field-effect transistor and method of forming the same
Tzu Ang Chiang, I-lan (TW); Ming-Hsi Yeh, Hsinchu (TW); Chun-Neng Lin, Hsinchu (TW); Jian-Jou Lian, Tainan (TW); Po-Yuan Wang, Hsinchu (TW); and Chieh-Wei Chen, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 29, 2023, as Appl. No. 18/344,554.
Application 18/344,554 is a continuation of application No. 17/688,364, filed on Mar. 7, 2022, granted, now 11,735,425.
Application 17/688,364 is a continuation of application No. 16/859,538, filed on Apr. 27, 2020, granted, now 11,309,185, issued on Apr. 19, 2022.
Prior Publication US 2023/0352306 A1, Nov. 2, 2023
Int. Cl. H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/28132 (2013.01) [H01L 21/28088 (2013.01); H01L 21/31111 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor fin;
a metal gate disposed over the semiconductor fin;
a gate dielectric layer disposed between the semiconductor fin and the metal gate;
spacers sandwiching the metal gate, wherein the spacers include a first spacer contacting the gate dielectric layer and a second spacer contacting the first spacer, the first spacer and the second spacer having different heights; and
a gate electrode contacting the metal gate and the gate dielectric layer at a first interface and a second interface, respectively, wherein the first interface is below the second interface, and wherein a top surface of the gate electrode is above a top surface of the gate dielectric layer, wherein a top surface of the first spacer is below the top surface of the gate electrode, and wherein a top surface of the second spacer is above the top surface of the gate electrode.