	US 12,080,379 B2
	Semiconductor device
Baek Jin Lim, Suwon-si (KR); Youngchul Cho, Gyeonggi-do (KR); Seungjin Park, Suwon-si (KR); Doobock Lee, Gyeonggi-do (KR); Youngdon Choi, Seoul (KR); and Junghwan Choi, Gyeonggi-do (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 7, 2022, as Appl. No. 17/939,016.
Claims priority of application No. 10-2022-0005468 (KR), filed on Jan. 13, 2022; and application No. 10-2022-0049002 (KR), filed on Apr. 20, 2022.
Prior Publication US 2023/0223060 A1, Jul. 13, 2023
Int. Cl. G11C 7/22 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01)

CPC G11C 7/222 (2013.01) [G11C 7/06 (2013.01); G11C 7/1096 (2013.01)]

20 Claims

1. A semiconductor device comprising:

a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of the plurality of divided clock signals; and

a calibration circuit configured to:

apply a first offset clock signal among the plurality of offset clock signals to a first sampler circuit among the plurality of sampler circuits,

apply a second offset clock signal, among the plurality of offset clock signals, having an opposite phase to the first offset clock signal to a second sampler circuit among the plurality of sampler circuits, and

generate a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.