US 12,080,378 B2
Circuits and methods of detecting at least partial breakdown of canary circuits
Fernando García Redondo, Cambridge (GB); Pranay Prabhat, Cambridge (GB); Mudit Bhargava, Austin, TX (US); and Supreet Jeloka, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Mar. 30, 2022, as Appl. No. 17/709,076.
Prior Publication US 2023/0317126 A1, Oct. 5, 2023
Int. Cl. G11C 7/12 (2006.01); G11C 5/12 (2006.01); G11C 7/16 (2006.01); G11C 7/18 (2006.01); G11C 8/08 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 5/12 (2013.01); G11C 7/16 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A circuit comprising:
a memory array comprising one or more groupings of bitcells, one or more bitlines, and one or more wordlines; and
one or more canary circuits coupled to the memory array, wherein each of the canary circuits is configured to predict at least partial breakdown of a corresponding grouping of bitcells in the memory array, and
wherein each of the one or more canary circuits are activated by a substantially similar wordline voltage, wherein the wordline voltage is a negative voltage, wherein an absolute value of the negative voltage is less than a voltage threshold, and wherein the voltage threshold corresponds to a rate of voltage discharge of a bitline to allow a time-to-digital converter (TDC) or counter to detect a breakdown of at least one of the one or more canary circuits.