US 12,080,377 B2
Semiconductor device
Yuki Okamoto, Ebina (JP); Tatsuya Onuki, Atsugi (JP); Munehiro Kozuma, Atsugi (JP); and Takanori Matsuzaki, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/802,281
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Mar. 4, 2021, PCT No. PCT/IB2021/051788
§ 371(c)(1), (2) Date Aug. 25, 2022,
PCT Pub. No. WO2021/186279, PCT Pub. Date Sep. 23, 2021.
Claims priority of application No. 2020-047259 (JP), filed on Mar. 18, 2020.
Prior Publication US 2023/0099168 A1, Mar. 30, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01)
CPC G11C 7/1096 (2013.01) [G11C 7/12 (2013.01); G11C 8/08 (2013.01); H01L 29/7869 (2013.01); H10B 12/31 (2023.02); H10B 12/50 (2023.02)] 21 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a plurality of arithmetic blocks,
wherein one of the plurality of arithmetic blocks comprises an arithmetic circuit portion in a first layer and a memory circuit portion in a second layer,
wherein the arithmetic circuit portion comprises a first driver circuit, a second driver circuit and a third driver circuit in the first layer,
wherein each of the first driver circuit, the second driver circuit and the third driver circuit is electrically connected to the memory circuit portion, and
wherein the memory circuit portion and each of the first driver circuit, the second driver circuit and the third driver circuit overlap each other.