US 12,080,375 B2
Circuits and methods for compensating a mismatch in a sense amplifier
Ku-Feng Lin, New Taipei (TW); Yu-Der Chih, Hsin-Chu (TW); Yi-Chun Shih, Taipei (TW); and Chia-Fu Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/232,768.
Application 18/232,768 is a continuation of application No. 17/737,734, filed on May 5, 2022, granted, now 11,783,873.
Application 17/737,734 is a continuation of application No. 17/156,383, filed on Jan. 22, 2021, granted, now 11,373,690.
Application 17/156,383 is a continuation of application No. 16/400,222, filed on May 1, 2019, granted, now 10,957,366.
Claims priority of provisional application 62/675,947, filed on May 24, 2018.
Prior Publication US 2023/0386528 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 11/14 (2006.01); G11C 13/00 (2006.01); H01L 27/10 (2006.01)
CPC G11C 7/065 (2013.01) [G11C 7/08 (2013.01); G11C 11/14 (2013.01); G11C 13/004 (2013.01); H01L 27/10 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a first branch comprising a first plurality of transistors, a first memory bit cell, a first clamping transistor coupled to the first memory bit cell;
a second branch comprising a second plurality of transistors, a second memory bit cell, a second clamping transistor coupled to the second memory bit cell;
a first plurality of trimming transistors that are connected in parallel to each other and connected in parallel to at least one of the first plurality of transistors; and
a second plurality of trimming transistors that are connected in parallel to each other and connected in parallel to at least one of the second plurality of transistors.