| CPC G11C 7/065 (2013.01) [G11C 7/12 (2013.01); G11C 7/222 (2013.01)] | 19 Claims |
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1. A semiconductor storage device comprising:
a memory string;
a bit line connected to the memory string;
a sense amplifier connected to the bit line;
first, second, third, and fourth latch circuits that are each connected to the sense amplifier;
a first wiring connected to the sense amplifier, the first latch circuit, and the second latch circuit;
a second wiring connected to the third latch circuit;
a third wiring connected to the fourth latch circuit;
a first switch transistor between the first wiring and the third wiring;
a second switch transistor between the first wiring and the second wiring; and
a third switch transistor between the second wiring and the third wiring.
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