US 12,080,372 B2
System and method of power management in memory design
He-Zhou Wan, Hsinchu (TW); Xiuli Yang, Hsinchu (TW); Ming-En Bu, Hsinchu (TW); Mengxiang Xu, Hsinchu (TW); and Zong-Liang Cao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY, LIMITED, Shanghai (CN)
Filed on Dec. 9, 2022, as Appl. No. 18/064,048.
Application 18/064,048 is a continuation of application No. 17/185,030, filed on Feb. 25, 2021, granted, now 11,545,192.
Claims priority of application No. 202110163497.9 (CN), filed on Feb. 5, 2021.
Prior Publication US 2023/0105283 A1, Apr. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/14 (2006.01)
CPC G11C 5/148 (2013.01) 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first virtual power line, in a first memory bank, configured to be coupled to a power supply through a first group of transistor switches;
a second virtual power line, in a second memory bank, configured to receive the power supply through a second group of transistor switches;
a first delay circuit having a first input coupled to gate terminals of the first group of transistor switches and having a first output coupled to gate terminals in the second group of transistor switches;
a first wakeup detector configured to generate a first trigger signal after receiving a signal from the first output of the first delay circuit; and
a plurality of main input-output (MIO) controllers configured to be coupled to the power supply through a first group of wakeup switches and through a first group of function switches, wherein gate terminals in the first group of wakeup switches are configured to receive the first trigger signal.