US 12,080,371 B2
SRAM power switching with reduced leakage, noise rejection, and supply fault tolerance
Pietro Caragiulo, Palo Alto, CA (US); and Daniel Henry Morris, Mountain View, CA (US)
Assigned to META PLATFORMS TECHNOLOGIES, LLC, Menlo Park, CA (US)
Filed by Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed on Aug. 19, 2022, as Appl. No. 17/891,858.
Prior Publication US 2024/0062787 A1, Feb. 22, 2024
Int. Cl. G11C 5/14 (2006.01); G11C 11/412 (2006.01)
CPC G11C 5/147 (2013.01) [G11C 11/4125 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a static random access memory (SRAM) array comprising a plurality of SRAM bit cells;
power switching logic configured to generate a supply voltage for the SRAM array, wherein:
the power switching logic generates the supply voltage using a first supply rail during an active state and using a second supply rail during a deep retention state,
the first supply rail supplies a first voltage, and
the second supply rail supplies a second voltage that is lower than the first voltage; and
a sensing and recovery (SR) unit configured to:
sense a decrease in the second voltage during the deep retention state; and
generate an additional voltage based on the decrease in the second voltage, wherein the additional voltage modifies the supply voltage generated by the power switching logic such that the supply voltage, as modified by the additional voltage, is higher than the decreased second voltage.