| CPC G11C 5/06 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
a memory cell array that includes:
a plurality of pieces of gate wiring, and
a plurality of memory cell transistors and a plurality of select transistors electrically connected to the plurality of pieces of gate wiring; and
a test control circuit that includes a plurality of control units electrically connected to the plurality of pieces of gate wiring, the test control circuit configured to control discharging of the plurality of pieces of gate wiring during a test of the memory cell array, wherein
the control units each include:
a field effect transistor that includes:
a gate electrically connected to a first node,
one end electrically connected to at least one corresponding piece among the plurality of pieces of gate wiring, and
another end electrically connected to a second node that is grounded, and
a load unit that is electrically connected between the first node and the second node,
when the plurality of pieces of gate wiring are being discharged, the field effect transistor is set as an on state,
the plurality of pieces of gate wiring each are electrically connected to the second node via the field effect transistor in the on state, and
the load unit discharges the first node after the plurality of pieces of gate wiring are discharged.
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