US 12,080,367 B2
Memory and operation method thereof including accessing redundancy world lines by memory controller
Woo-Hyun Paik, Seoul (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Oct. 8, 2019, as Appl. No. 16/596,368.
Claims priority of application No. 10-2019-0019769 (KR), filed on Feb. 20, 2019.
Prior Publication US 2020/0265916 A1, Aug. 20, 2020
Int. Cl. G11C 29/00 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01)
CPC G11C 29/883 (2013.01) [G11C 8/08 (2013.01); G11C 8/10 (2013.01)] 10 Claims
OG exemplary drawing
 
1. An operation method of a memory including normal word lines and redundancy word lines for replacing failed word lines among the normal word lines according to row redundancy information, the operation method comprising:
receiving from a memory controller, a row address, data to be written to the memory, an active command instructing activation of the memory, the row redundancy information, and a flag signal;
determining whether the flag signal is activated or deactivated;
decoding, when the flag signal is deactivated, the row address which is received through address pads during a row activation operation which, with the flag deactivated, activates one of the normal word lines; and
decoding, when the flag signal is activated, the row redundancy information which is received through data I/O pads along with the active command and the data to be written to the memory during the row activation operation which, with the flag activated, activates one of the redundancy word lines,
wherein, during a write operation, the data to be written in the memory is received through the data I/O pads and written to the normal word lines or the redundancy word lines depending on the flag signal, wherein the flag signal is received through the data I/O pads, wherein the data I/O pads are separate from the address pads.