US 12,080,365 B2
Analog storage using memory device
Mattia Boniardi, Cormano (IT); and Innocenzo Tortorelli, Cernusco sul Naviglio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/048,669
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Jan. 28, 2020, PCT No. PCT/IB2020/000015
§ 371(c)(1), (2) Date Oct. 19, 2020,
PCT Pub. No. WO2021/152338, PCT Pub. Date Aug. 5, 2021.
Prior Publication US 2023/0114966 A1, Apr. 13, 2023
Int. Cl. G11C 27/00 (2006.01); G06N 3/065 (2023.01); G06N 3/08 (2023.01)
CPC G11C 27/005 (2013.01) [G06N 3/065 (2023.01); G06N 3/08 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A device, comprising:
a multi-deck memory array;
a plurality of respective memory cells, each memory cell in the respective memory cells having a programming sensitivity different from programming sensitivities of other memory cells in the respective memory cells, wherein the respective memory cells being on different decks of the multi-deck memory array; and
reading circuitry configured to read respective analog information programmed in the respective memory cells and to provide an output based on a combination of the respective analog information read from the respective memory cells, wherein the respective memory cells include a first memory cell and a second memory cell, comprising of different storage material;
a first storage element of the first memory cell comprises a first storage material; and a second storage element of the second memory cell comprises a second storage material different from the first storage material.