US 12,080,364 B2
Shift register and method for driving the same, gate driving circuit, and display device
Xuehuan Feng, Beijing (CN); and Yongqian Li, Beijing (CN)
Assigned to HEFEI BOE JOINT TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/791,597
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Dec. 26, 2020, PCT No. PCT/CN2020/139714
§ 371(c)(1), (2) Date Jul. 8, 2022,
PCT Pub. No. WO2022/134111, PCT Pub. Date Jun. 30, 2022.
Prior Publication US 2023/0335207 A1, Oct. 19, 2023
Int. Cl. G11C 19/28 (2006.01)
CPC G11C 19/287 (2013.01) [G09G 2310/0286 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register comprising
a first scan unit and a second scan unit, wherein the first scan unit includes a first input circuit and a first output circuit, wherein the first input circuit is electrically connected to an input signal terminal and a first pull-up node;
the first input circuit is configured to, in response to an input signal received at the input signal terminal, transmit the input signal to the first pull-up node; and
the first output circuit is electrically connected to the first pull-up node, a first clock signal terminal, a second clock signal terminal, a shift signal terminal, and a first scan signal terminal;
the first output circuit is configured to:
transmit a first clock signal received at the first clock signal terminal to the shift signal terminal under a control of a voltage of the first pull-up node, so that a shift signal is output from the shift signal terminal; and
transmit a second clock signal received at the second clock signal terminal to the first scan signal terminal under the control of the voltage of the first pull-up node, so that a first scan signal is output from the first scan signal terminal; and
the second scan unit includes a second input circuit, a second output circuit, and a potential boost circuit, wherein the second input circuit is electrically connected to the input signal terminal and a second pull-up node;
the second input circuit is configured to, in response to the input signal received at the input signal terminal, transmit the input signal to the second pull-up node;
the second output circuit is electrically connected to the second pull-up node, a third clock signal terminal, and a second scan signal terminal;
the second output circuit is configured to transmit a third clock signal received at the third clock signal terminal to the second scan signal terminal under a control of a voltage of the second pull-up node, so that a second scan signal is output from the second scan signal terminal; and
the potential boost circuit is electrically connected to the second pull-up node, a sub-clock signal terminal, and a dummy shift signal terminal, and the sub-clock signal terminal is the third clock signal terminal electrically connected to the second output circuit;
the potential boost circuit is configured to boost the voltage of the second pull-up node in cooperation with the second output circuit in a phase of outputting the second scan signal from the second scan signal terminal.