US 12,080,360 B2
Reducing programming disturbance in memory devices
Aaron Yip, Los Gatos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 9, 2023, as Appl. No. 18/195,181.
Application 18/195,181 is a continuation of application No. 17/751,131, filed on May 23, 2022, granted, now 11,688,470.
Application 17/751,131 is a continuation of application No. 17/157,443, filed on Jan. 25, 2021, granted, now 11,342,034.
Application 17/157,443 is a continuation of application No. 16/784,899, filed on Feb. 7, 2020, granted, now 10,902,927.
Application 16/784,899 is a continuation of application No. 15/451,022, filed on Mar. 6, 2017, granted, now 10,559,367.
Application 15/451,022 is a continuation of application No. 13/647,179, filed on Oct. 8, 2012, granted, now 9,589,644.
Prior Publication US 2023/0360710 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
programming a memory cell in a block of NAND memory cell strings, the block including multiple sub-blocks of memory cell strings, wherein the memory cell strings respectively comprise multiple NAND memory cells extending between a source select gate and a drain select gate and sharing a common channel material;
wherein the programming of a selected NAND memory cell in a selected NAND memory cell string in a selected sub-block, comprises:
during a first interval of a programming operation, precharging channel material of memory cell strings in both the selected sub-block and in at least one unselected sub-block to a precharge voltage, wherein the at least one unselected sub-block does not contain a selected memory cell; and
during a second interval of the programming operation, after the first interval, applying a programming voltage to a first access line coupled to the selected memory cell in the selected sub-block, wherein an unselected memory cell in the at least one unselected sub-block is also coupled to the first access line;
wherein during the second interval of the programming operation, the channel materials of a group of memory cell strings in the unselected sub-block are charged to a first voltage higher than the precharge voltage by a voltage induced on the channel materials of the group of memory cell strings in the unselected sub-block as a result of the programming voltage on the first access line.