US 12,080,356 B2
Methods of forming integrated circuit structures for capacitive sense NAND memory
Yoshiaki Fukuzumi, Yokohama (JP); Jun Fujiki, Tokyo (JP); Shuji Tanaka, Kanagawa (JP); Masashi Yoshida, Yokohama (JP); Masanobu Saito, Chiba (JP); and Yoshihiko Kamata, Yokohama (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 29, 2022, as Appl. No. 17/876,718.
Application 17/876,718 is a continuation of application No. 17/111,729, filed on Dec. 4, 2020, granted, now 11,437,106.
Prior Publication US 2022/0383960 A1, Dec. 1, 2022
Int. Cl. G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/0483 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit structure for a capacitive sense NAND memory, the method comprising:
forming a first semiconductor overlying a dielectric;
forming a second semiconductor to be in contact with a first end of the first semiconductor, and forming a third semiconductor to be in contact with a second end of the first semiconductor opposite the first end of the first semiconductor;
forming a vertical channel material structure overlying the first semiconductor and having a channel material capacitively coupled to the first semiconductor; and
forming a plurality of series-connected field-effect transistors adjacent the vertical channel material structure.