US 12,080,354 B2
Nonvolatile semiconductor memory device which performs improved erase operation
Jun Nakai, Yokohama (JP); and Noboru Shibata, Kawasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Apr. 17, 2023, as Appl. No. 18/301,800.
Application 18/301,800 is a division of application No. 17/344,146, filed on Jun. 10, 2021, granted, now 11,664,077.
Application 16/180,541 is a division of application No. 15/666,114, filed on Aug. 1, 2017, granted, now 10,157,675, issued on Dec. 18, 2018.
Application 17/344,146 is a continuation of application No. 16/871,578, filed on May 11, 2020, granted, now 11,062,777, issued on Jul. 13, 2021.
Application 16/871,578 is a continuation of application No. 16/180,541, filed on Nov. 5, 2018, granted, now 10,685,715, issued on Jun. 16, 2020.
Application 15/666,114 is a continuation of application No. 15/245,892, filed on Aug. 24, 2016, granted, now 9,754,672, issued on Sep. 5, 2017.
Application 15/245,892 is a continuation of application No. 14/677,484, filed on Apr. 2, 2015, granted, now 9,437,308, issued on Sep. 6, 2016.
Application 14/677,484 is a continuation of application No. 14/022,944, filed on Sep. 10, 2013, granted, now 9,025,390, issued on May 5, 2015.
Application 14/022,944 is a continuation of application No. 13/052,158, filed on Mar. 21, 2011, granted, now 8,559,236, issued on Oct. 15, 2013.
Claims priority of application No. 2010-182485 (JP), filed on Aug. 17, 2010.
Prior Publication US 2023/0260577 A1, Aug. 17, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/344 (2013.01); G11C 16/3445 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device comprising:
a bit line;
a plurality of first word lines;
a plurality of second word lines;
a source line;
a memory block including a plurality of memory cells connected in series, the memory cells including:
a first part of the memory cells, to gates of which the first word lines are connected, respectively; and
a second part of the memory cells, to gates of which the second word lines are connected, respectively, the second part of the memory cells functioning as dummy memory cells; and
a control unit configured to:
perform an erase operation upon receipt of an erase command, the erase operation including:
a plurality of erase voltage apply steps applied to the first part of the memory cells and the second part of the memory cells;
a plurality of erase verify steps applied to the first part of the memory cells and the second part of the memory cells, the erase verify steps each performed after a corresponding one of the erase voltage apply steps;
a soft program step applied only to the second part of the memory cells; and
a soft program verify step applied only to the second part of the memory cells, the soft program verify step performed after the soft program step;
suspend the erase operation upon receipt of a suspend command during performing one of the erase voltage apply steps, the erase operation being suspended at completion of one of the erase voltage apply steps;
perform a first operation upon receipt of a first command, an operation time of the erase operation being longer than an operation time of the first operation; and
resume the erase operation upon receipt of a resume command, the erase operation being resumed at start of one of the erase verify steps.