US 12,080,353 B2
Semiconductor device and erasing method
Masaru Yano, Kanagawa (JP); and Toshiaki Takeshita, Kanagawa (JP)
Assigned to Winbond Electronics Corp., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Nov. 17, 2022, as Appl. No. 17/988,782.
Claims priority of application No. 2021-199805 (JP), filed on Dec. 9, 2021.
Prior Publication US 2023/0186997 A1, Jun. 15, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/16 (2013.01) [G11C 16/0483 (2013.01); G11C 16/3445 (2013.01)] 13 Claims
OG exemplary drawing
 
8. A semiconductor device, comprising a NAND memory cell array; and
an erasing component erasing a selected block of the memory cell array,
wherein the erasing component performs a first erasing verification on the selected block with a first readout voltage, performs a second erasing verification with a second readout voltage lower than the first readout voltage, controls a next erase pulse to be applied based on the first erasing verification and the second erasing verification, and applies an erase pulse with a same erase voltage as last time between thresholds specified by the first erasing verification and the second erasing verification.