| CPC G11C 16/16 (2013.01) [G11C 16/08 (2013.01); G11C 16/3495 (2013.01); G11C 29/52 (2013.01)] | 10 Claims |
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1. A memory system comprising:
a nonvolatile memory; and
a controller configured to execute writing of data to the nonvolatile memory and reading of data from the nonvolatile memory, wherein
the nonvolatile memory includes a plurality of blocks, each of the plurality of blocks being a unit for an erase operation,
each of the plurality of blocks includes a plurality of memory cells connected to each of a plurality of word lines, and
the controller is configured to:
manage a plurality of word line groups, each of the plurality of word line groups including one or more word lines of the plurality of word lines; and
each time the number of program/erase cycles of a first block among the plurality of blocks increases by a first number of times:
measure the number of error bits of data read from a plurality of memory cells connected to each of a plurality of word lines of the first block;
identify a first word line group among the plurality of word line groups, the first word line group including a word line corresponding to the number of error bits which is greater than a threshold;
calculate an average number of error bits indicating an average of the numbers of error bits of one or more word lines included in the first word line group;
select, based on the average number of error bits of the first word line group, a parameter set to be applied to the first word line group from a plurality of parameter sets, each of the plurality of parameter set defining a program operation of the nonvolatile memory; and
change, to the selected parameter set, a parameter set defining the program operation for each of the one or more word lines included in the first word line group of the first block.
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