CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/34 (2013.01)] | 20 Claims |
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
receiving a request to program data to a block of the memory array, the block comprising a plurality of sub-blocks;
identifying a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data;
causing a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block; and
causing a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.
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