US 12,080,351 B2
Using non-segregated cells as drain-side select gates for sub-blocks in a memory device
Aaron S. Yip, Los Gatos, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 14, 2022, as Appl. No. 17/944,940.
Claims priority of provisional application 63/262,204, filed on Oct. 7, 2021.
Prior Publication US 2023/0112381 A1, Apr. 13, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array; and
control logic, operatively coupled with the memory array, to perform operations comprising:
receiving a request to program data to a block of the memory array, the block comprising a plurality of sub-blocks;
identifying a first sub-block of the plurality of sub-blocks to be programmed with at least a portion of the data;
causing a plurality of control signals to be applied to a plurality of logical select gate layers positioned at a drain-side of the block to activate the first sub-block; and
causing a program signal to be applied to a selected wordline of the block to program at least the portion of the data to a memory cell in the first sub-block and associated with the selected wordline.