	US 12,080,350 B2
	Balancing data in memory
Marco Sforzin, Cernusco Sul Naviglio (IT); and Riccardo Muzzetto, Arcore (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 18, 2022, as Appl. No. 17/890,912.
Prior Publication US 2024/0062824 A1, Feb. 22, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)

CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01)]

26 Claims

1. An apparatus, comprising:

a memory having a group of memory cells, wherein each respective memory cell of the group is programmable to one of three possible data states; and

circuitry configured to balance data programmed to the group of memory cells between the three possible data states by:

determining whether the data programmed to the group of memory cells is balanced for any one of the three possible data states; and

upon determining the data programmed to the group of memory cells is not balanced for any one of the three possible data states:

apply a rotational mapping algorithm to the data programmed to the group of memory cells until the data is balanced for any one of the three possible data states; and

apply a Knuth algorithm to the data of the group of memory cells programmed to the two of the three possible data states that were not balanced by the rotational mapping algorithm.