| CPC G11C 15/04 (2013.01) | 20 Claims |
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1. A semiconductor device, comprising:
a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction;
a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate;
a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line, and electrically connected to the first and second memory cells;
first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer;
first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line;
second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and
a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.
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