US 12,080,347 B1
Differential programming of two-terminal resistive switching memory with program soaking and adjacent path disablement
Hagop Nazarian, San Jose, CA (US)
Assigned to CROSSBAR, INC., Santa Clara, CA (US)
Filed by Crossbar, Inc., Santa Clara, CA (US)
Filed on Mar. 31, 2022, as Appl. No. 17/710,835.
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 13/004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
an array of two-terminal resistive switching memory comprising:
a first bitline;
a second bitline;
a first two-terminal resistive switching memory comprising a first terminal electrically connected to the first bitline, and a second terminal;
a second two-terminal resistive switching memory comprising a first terminal electrically connected to the second bitline, and a second terminal;
a voltage source;
a first switch for selectively connecting or disconnecting the first bitline and the second bitline to or from the voltage source;
a second switch for selectively connecting or disconnecting the second terminal of the first two-terminal resistive switching memory and the second terminal of the second two-terminal resistive switching memory to or from low voltage, or ground;
a detection circuit configured to detect a program event for the first two-terminal resistive switching memory or for the second two-terminal resistive switching memory; and
a termination circuit configured to at least one of:
disconnect the first bitline from the voltage source in response to the detection circuit detecting the program event for the second two-terminal resistive switching memory, or
disconnect the second bitline from the voltage source in response to the detection circuit detecting the program event for the first two-terminal resistive switching memory.