a bank layer arranged on a semiconductor substrate, the bank layer including a plurality of mats, each of the mats including a plurality of stacked decks, and each of the decks including a plurality of memory cells; and

a control circuit layer arranged between the semiconductor substrate and the bank layer, the control circuit layer including a plurality of control circuit regions corresponding to the mats,

wherein the plurality of the stacked decks comprises a plurality of stacked word lines, a plurality of stacked bit lines intersected with the stacked word lines, and

wherein a word line decoder for controlling the stacked word lines and a bit line decoder for controlling the stacked bit lines are respectively located in the control circuit regions and the word line decoder and bit line decoder are alternately arranged in the control circuit layer along a word line extension direction and a bit line extension direction,

wherein the stacked word lines are divided by a length between a pair of the adjacent word line decoders in a row direction parallel with the word line extension direction to form a plurality of word line stack structures, and

wherein the stacked bit lines are divided by a length between a pair of the adjacent bit line decoders in a column direction parallel with the bit line extension direction to form a plurality of bit line stack structures.