CPC G11C 11/5692 (2013.01) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] | 9 Claims |
1. A multi-bit, asynchronous e-fuse macro, the macro comprising:
the following inputs: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock;
a plurality of e-fuse bits, wherein each e-fuse bit comprises at least one radiation hardened latch;
a supply voltage configured to allow programming at least one of the e-fuse bits;
at least one fuse output; and
self-timing and control circuitry configured to perform signaling,
wherein each of the inputs is in electrical communication with said e-fuse macro;
wherein the write address is a variable width bus configured to provide a plurality of write address bits; and
wherein the asynchronous e-fuse macro is configured to:
receive power from the supply voltage when the supply voltage is either floating or grounded;
assert reset, precharge, output enable, and ground clamp while de-asserting read enable, hold, and write enable and disabling read reference current;
de-assert reset while enabling read reference current;
de-assert precharge while asserting read enable;
pulse hold, thereby storing e-fuse memory element values in the at least one latch;
assert precharge while de-asserting read enable; and
disable read reference current.
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