US 12,080,342 B2
Static random access memory (SRAM) with a pre- charge assist circuit
Chia-Hao Pao, Kaohsiung (TW); Kian-Long Lim, Hsinchu (TW); Chih-Chuan Yang, Hsinchu (TW); Jui-Wen Chang, Hsinchu (TW); Chao-Yuan Chang, New Taipei (TW); Feng-Ming Chang, Zhubei (TW); Lien-Jung Hung, Taipei (TW); and Ping-Wei Wang, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 18, 2022, as Appl. No. 17/698,681.
Claims priority of provisional application 63/212,271, filed on Jun. 18, 2021.
Prior Publication US 2022/0406372 A1, Dec. 22, 2022
Int. Cl. G11C 11/419 (2006.01)
CPC G11C 11/419 (2013.01) 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array comprising a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns, wherein each of the plurality of columns comprises a first plurality of memory cells connected to a first bit line and a second bit line;
a pre-charge circuit connected to the memory cell array, wherein the pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end; and
a pre-charge assist circuit connected to the memory cell array, wherein the pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.