US 12,080,336 B2
Apparatuses and methods for compensated sense amplifier with cross coupled N-type transistors
Jiyun Li, Boise, ID (US); Christopher J. Kawamura, Boise, ID (US); and Tae H. Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on May 5, 2022, as Appl. No. 17/662,198.
Prior Publication US 2023/0360690 A1, Nov. 9, 2023
Int. Cl. G11C 11/4091 (2006.01); H03F 3/45 (2006.01)
CPC G11C 11/4091 (2013.01) [H03F 3/45264 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first digit line;
a second digit line;
a first gut node;
a second gut node;
a first transistor configured to couple a first voltage to the first gut node based on a voltage on the second digit line;
a second transistor configured to couple the first voltage to the second gut node based on a voltage on the first digit line, wherein the first and the second transistors are p-type transistors and wherein the first and the second transistors are configured to be coupled in a diode fashion when a command signal is active;
a third transistor configured to couple the first gut node to a second voltage based on a voltage on the second gut node;
a fourth transistor configured to couple the second gut node to the second voltage based on a voltage on the first gut node, wherein the third and the fourth transistors are n-type;
a first bit line clamp (BLCP) transistor configured to short the first gut node to the second digit line when the command signal is active; and
a second BLCP transistor configured to short the second gut node to the first digit line when the command signal is active.