US 12,080,335 B2
Signal sampling circuit and semiconductor memory
Zequn Huang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 21, 2022, as Appl. No. 17/934,185.
Application 17/934,185 is a continuation of application No. PCT/CN2022/091428, filed on May 7, 2022.
Claims priority of application No. 202210294955.7 (CN), filed on Mar. 23, 2022.
Prior Publication US 2023/0009525 A1, Jan. 12, 2023
Int. Cl. G11C 11/4076 (2006.01); H03K 3/037 (2006.01); H03K 5/135 (2006.01); H03K 19/20 (2006.01)
CPC G11C 11/4076 (2013.01) [H03K 3/037 (2013.01); H03K 5/135 (2013.01); H03K 19/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A signal sampling circuit, comprising a signal input circuit, a first instruction sampling circuit, a second instruction sampling circuit, and an instruction decoding circuit, wherein
the signal input circuit is configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal according to a first clock signal, a first chip select signal, and a first command address signal, wherein a clock cycle of the first clock signal is twice a preset clock cycle;
the first instruction sampling circuit is configured to perform, responsive to a pulse width of the first chip select signal being the preset clock cycle, two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal, to obtain a first chip select clock signal;
the second instruction sampling circuit is configured to perform, responsive to the pulse width of the first chip select signal being twice the preset clock cycle, two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal, to obtain a second chip select clock signal; and
the instruction decoding circuit is configured to perform decoding and sampling processing on the to-be-processed instruction signal according to the to-be-processed chip select signal and the first chip select clock signal to obtain a target instruction signal, or perform decoding and sampling processing on the to-be-processed instruction signal according to the to-be-processed chip select signal and the second chip select clock signal to obtain the target instruction signal.