an operation period adjusting circuit configured to generate operation information for adjusting an operation period, when an input count of an active command during a test mode period is equal to or more than a preset count;

a command generation circuit configured to adjust the input count of the active command applied to a semiconductor device during a preset period, by adjusting the operation period on the basis of the operation information, and

wherein the operation period is set to a time period from a point of time that the active command is generated to a point of time that a precharge command is generated, and

wherein the operation period adjusting circuit comprises:

a test control circuit configured to generate a period signal for setting the test mode period by counting pulses of a clock;

an active counting circuit configured to generate an operation control signal which is generated when the input count of the active command from a point of time that a first pulse of the period signal is input to a point of time that a second pulse of the period signal is input is equal to or more than the preset count; and

an operation information generation circuit configured to generate the operation information for adjusting the operation period on the basis of the operation control signal.