US 12,080,332 B2
Memory device, a memory system having the same and an operating method thereof in which a row address is not separated depending on pages in a byte mode operation
Seungki Hong, Incheon (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 7, 2022, as Appl. No. 17/834,320.
Claims priority of application No. 10-2021-0151056 (KR), filed on Nov. 5, 2021.
Prior Publication US 2023/0143468 A1, May 11, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/40603 (2013.01); G11C 11/40622 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An operating method of a memory device, the method comprising:
receiving a row address;
determining whether an operating mode is a byte mode;
counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode;
selecting a target row hammer address, among target row addresses, using access count values for the target row hammer address;
calculating a victim row address corresponding to the target row hammer address; and
performing a target refresh operation on the victim row address.