US 12,080,330 B2
Memory array with compensated word line access delay
Si Hong Kim, Boise, ID (US); and John D. Porter, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 31, 2022, as Appl. No. 17/899,859.
Prior Publication US 2024/0071456 A1, Feb. 29, 2024
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01); G11C 11/2257 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first word line;
a second word line;
a first digit line;
a plurality of memory cells, wherein a first memory cell of the plurality of memory cells is coupled to the first word line and the first digit line, and a second memory cell of the plurality of memory cells is coupled to the second word line and the first digit line; and
a first sense amplifier coupled to the first digit line, the first sense amplifier comprising:
a first reference capacitor coupled to the first digit line;
a second reference capacitor coupled to the first digit line;
switching circuitry coupled to the first reference capacitor and the second reference capacitor, the switching circuitry configured to:
receive a reference voltage;
provide the reference voltage to the first reference capacitor when the first memory cell is activated; and
provide the reference voltage to the second reference capacitor when the second memory cell is activated; and
first latching circuitry coupled to the first digit line.