US 12,080,254 B2
Method for driving semiconductor device
Hajime Kimura, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 28, 2023, as Appl. No. 18/141,029.
Application 18/141,029 is a continuation of application No. 17/944,224, filed on Sep. 14, 2022, granted, now 11,670,251.
Application 17/944,224 is a continuation of application No. 17/338,465, filed on Jun. 3, 2021, granted, now 11,450,291, issued on Sep. 20, 2022.
Application 17/338,465 is a continuation of application No. 15/931,960, filed on May 14, 2020, granted, now 11,030,966, issued on Jun. 8, 2021.
Application 15/931,960 is a continuation of application No. 15/979,003, filed on May 14, 2018, granted, now 10,657,910, issued on May 19, 2020.
Application 15/979,003 is a continuation of application No. 15/148,351, filed on May 6, 2016, granted, now 9,978,320, issued on May 22, 2018.
Application 15/148,351 is a continuation of application No. 14/311,479, filed on Jun. 23, 2014, granted, now 9,343,018, issued on May 17, 2016.
Application 14/311,479 is a continuation of application No. 12/754,731, filed on Apr. 6, 2010, granted, now 8,780,034, issued on Jul. 15, 2014.
Claims priority of application No. 2009-094306 (JP), filed on Apr. 8, 2009.
Prior Publication US 2023/0274716 A1, Aug. 31, 2023
Int. Cl. G09G 3/36 (2006.01); G09G 3/34 (2006.01); G09G 5/10 (2006.01); H04N 5/208 (2006.01)
CPC G09G 3/3607 (2013.01) [G09G 3/3406 (2013.01); G09G 3/36 (2013.01); G09G 3/3614 (2013.01); G09G 3/3685 (2013.01); G09G 5/10 (2013.01); G09G 3/3413 (2013.01); G09G 2300/0452 (2013.01); G09G 2320/0233 (2013.01); H04N 5/208 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first circuit configured to perform frame interpolation processing, image analysis processing, or edge enhancement processing; and
a second circuit and a third circuit each configured to perform super-resolution processing or edge enhancement processing,
wherein an image source is input to an input terminal of the first circuit,
wherein an output terminal of the first circuit is electrically connected to an input terminal of the second circuit through a first switch,
wherein the output terminal of the first circuit is electrically connected to an input terminal of the third circuit through a second switch,
wherein an output terminal of the second circuit is electrically connected to a third switch,
wherein an output terminal of the third circuit is electrically connected to a fourth switch, and
wherein the first circuit, the second circuit, and the third circuit are performed concurrently by controlling the first switch, the second switch, the third switch, and the fourth switch.