a display panel comprising pixels electrically coupled to gate lines;

a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal, the common signal for determining a timing at which a black data signal is stored in at least some of the pixels;

a clock generator configured to generate clock signals having different phases based on the on-clock signal and the off-clock signal in a first period in which the enable signal has a first voltage level, and to generate the clock signals having a same phase based on the common signal in a second period in which the enable signal has a second voltage level different from the first voltage level; and

a gate driver configured to generate gate signals based on the clock signals, and to sequentially provide the gate signals to the gate lines,

wherein the on-clock signal and the off-clock signal have a same waveform having different phases,

wherein the on-clock signal in the first period is substantially the same as the on-clock signal in the second period, and

wherein the off-clock signal in the first period is substantially the same as the off-clock signal in the second period.