	US 12,079,896 B2
	Dynamic clock and voltage scaling (DCVS) lookahead bandwidth voting using feedforward compression ratio
Prashant Dinkar Karandikar, Bangalore (IN); Pradeep Venkatasubbarao, Bangalore (IN); Manmohan Manoharan, Bengaluru (IN); Vivekanandan Naveen, Bangalore (IN); Nagashree Ganapati Upadhya, Bangalore (IN); Shubham Sangal, Bangalore (IN); Srinivas Turaga, Bangalore (IN); and Shreya Pandurang Math, Dombivili (IN)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM INCORPORATED, San Diego, CA (US)
Filed on May 3, 2022, as Appl. No. 17/736,030.
Prior Publication US 2023/0360166 A1, Nov. 9, 2023
Int. Cl. G06T 1/20 (2006.01); G06F 1/08 (2006.01); G06T 1/60 (2006.01)

CPC G06T 1/20 (2013.01) [G06F 1/08 (2013.01); G06T 1/60 (2013.01)]

34 Claims

1. A system for dynamic clock and voltage scaling (DCVS) bandwidth voting, comprising:

a pipeline comprising a plurality of image processing components, a first image processing component in the pipeline is configured to determine a feedforward compression ratio based on a current frame of an image, the plurality of image processing components including a plurality of transaction initiator components, each transaction initiator component of the plurality of transaction initiator components is configured to select a bandwidth vote during the image processing and to transmit the bandwidth vote to a bandwidth aggregator during the image processing, each transaction initiator component selects the bandwidth vote during image processing by determining if the feedforward compression ratio-based value has changed; and

the bandwidth vote aggregator configured to determine a DCVS level based bandwidth votes received from each of the plurality of transaction initiator components.